NFG Games + GameSX

All information on this page was taken from: http://www.cityfujisawa.ne.jp/~akitsura/connect/X68_ex.html

X68000 I/O Expansion Slot

	Side A			Side B
	GND	1	51	GND
20MHz Clock	20M	2	52	10M	10MHz Clock
	GND	3	53	10M	10MHz Clock
Data Bus	DB00	4	54	E	Enable
Data Bus	DB01	5	55	AB00	Address Bus
Data Bus	DB02	6	56	AB01	Address Bus
Data Bus	DB03	7	57	AB02	Address Bus
Data Bus	DB04	8	58	AB03	Address Bus
Data Bus	DB05	9	59	AB04	Address Bus
Data Bus	DB06	10	60	AB05	Address Bus
	GND	11	61	GND
Data Bus	DB07	12	62	AB06	Address Bus
Data Bus	DB08	13	63	AB07	Address Bus
Data Bus	DB09	14	64	AB08	Address Bus
Data Bus	DB10	15	65	AB09	Address Bus
Data Bus	DB11	16	66	AB10	Address Bus
Data Bus	DB12	17	67	AB11	Address Bus
Data Bus	DB13	18	68	AB12	Address Bus
Data Bus	DB14	19	69	AB13	Address Bus
Data Bus	DB15	20	70	AB14	Address Bus
	GND	21	71	GND
+12V	+12V	22	72	AB15	Address Bus
+12V	+12V	23	73	AB16	Address Bus
CPU Function Code	FC0	24	74	AB17	Address Bus
CPU Function Code	FC1	25	75	AB18	Address Bus
CPU Function Code	FC2	26	76	AB19	Address Bus
Address Bus Confirm	AS	27	77	AB20	Address Bus
Lower Data Strobe	LDS	28	78	AB21	Address Bus
Upper Data Strobe	UDS	29	79	AB22	Address Bus
Transfer Direction	R/W	30	80	AB23	Address Bus
	GND	31	81	GND
-12V	-12V	32	82	HSYNC	Horizontal Sync
-12V	-12V	33	83	VSYNC	Vertical Sync
Address Bus Valid	VMA	34	84	DONE	Transfer Complete (DMA)
Peripheral is addressed around 68000 family (???)	EXVPA	35	85	DTC	Transfer Complete Device (DMA)
Data Transfer Acknowledge	DTACK	36	86	EXREQ	External Request (DMA)
External Reset	EXRESET	37	87	EXACK	External Authorization (DMA)
In: CPU Halt, Out: System Stop	HALT	38	88	EXPCL	External Peripheral Control (DMA)
External Bus Error	EXBERR	39	89	EXOWN	External OWN (DMA)
External Power On	EXPW.ON	40	90	EXNMI	External NMI (DMA)
	GND	41	91	GND
+5V	Vcc2	42	92	IRQ2-n	Interrupt Request (n: slot 1 or 2)
+5V	Vcc2	43	93	IRQ4-n	Interrupt Request (n: slot 1 or 2)
Memory Row/Column Switch Signal	SELEN	44	94	IACK2-n	Interrupt Enable (n: slot 1 or 2)
Memory CAS Signal (Read)	CASRDEN	45	95	IACK4-n	Interrupt Enable (n: slot 1 or 2)
Memory CAS Signal (Write Lower)	CASWRL	46	96	BRn	Bus Request
Memory CAS Signal (Write Upper)	CASWRU	47	97	BGn	Bus Grant
Main Memory Refresh Cycle	INH2	48	98	BGACK	Bus Grant Acknowledge
+5V	Vcc1	49	99	Vcc1	+5V
+5V	Vcc1	50	100	Vcc1	+5V