Table of Contents
DMAC
The HD63450 has four DMA channels. On the X68000 channels #0, #1 and, #3 are assigned respectively to FD, HD, and ADPCM. Channel #2 REQ(DMA transfer request signal), ACK(response signal), and PCL (general purpose input signal) is available to the user. It can be used for transfers between memory and memory and between memory and expansion boards.
The registers for the DMAC exist starting at 0xE84000 and there are 0x40 bytes for each channel. GCR (General Control Register) is only available on channel #3.
Addresses
| Address | Channel |
|---|---|
| 0xE84000 | #0 |
| 0xE84040 | #1 |
| 0xE84080 | #2 |
| 0xE840C0 | #3 |
Register List
| Offset | Size | R/W | Description |
|---|---|---|---|
| +0x00 | 1.b | R/W | CSR - Channel Status Register |
| +0x01 | 1.b | R | CER - Channel Error Register |
| +0x02 | 1.w | — | |
| +0x04 | 1.b | R/W | DCR - Device Control Register |
| +0x05 | 1.b | R/W | OCR - Operation Control Register |
| +0x06 | 1.b | R/W | SCR - Sequence Control Register |
| +0x07 | 1.b | R/W | CCR - Channel Control Register |
| +0x08 | 1.w | — | |
| +0x0A | 1.w | R/W | MTC - Memory Transfer Control |
| +0x0C | 1.l | R/W | MAR - Memory Address Register |
| +0x10 | 1.l | — | |
| +0x14 | 1.l | R/W | DAR - Device Address Register |
| +0x18 | 1.w | — | |
| +0x1A | 1.w | R/W | BTC - Base Transfer Counter |
| +0x1C | 1.l | R/W | BAR - Base Address Register |
| +0x20 | 1.l | — | |
| +0x24 | 1.b | — | |
| +0x25 | 1.b | R/W | NIV - Normal Interrupt Vector |
| +0x26 | 1.b | — | |
| +0x27 | 1.b | R/W | EIV - Error Interrupt Vector |
| +0x28 | 1.b | — | |
| +0x29 | 1.b | R/W | MFC - Memory Function Code |
| +0x2A | 1.w | — | |
| +0x2C | 1.b | — | |
| +0x2D | 1.b | R/W | CPR - Channel Priority Register |
| +0x2E | 1.w | — | |
| +0x30 | 1.b | — | |
| +0x31 | 1.b | R/W | DFC - Device Function Code |
| +0x32 | 3.w | — | |
| +0x38 | 1.b | — | |
| +0x39 | 1.b | R/W | BFC - Base Function Code |
| +0x3A | 1.l | — | |
| +0x3E | 1.b | — | |
| +0x3F | 1.b | R/W | GCR - General Control Register |
Register Descriptions
CSR<BOOKMARK:csr> - Channel Status Register (+0x00)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| COC | BTC | NDT | ERR | ACT | DIT | PCT | PCS |
| Bits | Name | Description |
|---|---|---|
| 7 | COC | Channel Operation Complete %0: Channel operation incomplete %1: Channel operation complete |
| 6 | BTC | Block Transfer Complete %0: Block transfer incomplete %1: Block transfer complete |
| 5 | NDT | Normal Device Termination %0: Not stopped due to DONE signal %1: Stopped due to DONE signal |
| 4 | ERR | Error bit %0: No error %1: Error occurred (ERROR CODE bit contains error) |
| 3 | ACT | Channel Active %0: Channel inactive %1: Channel active |
| 2 | DIT | DONE Input Transition %0: No DONE input %1: There was a DONE input when the BTD bit of OCR was %1 |
| 1 | PCT | PCL Transition %0 There is no PCL transition (High→Low transition) %1: PCL transition occured |
| 0 | PCS | PCL Status Line %0: PCL = Low %1: PCL = high |
Note: When a bit other than ACT or PCS becomes %1 it remains %1 until %1 is written to that bit or a reset is applied. In particular it is necessary to clear COC, BTC, NDT, ERR, and ACT since it is not possible to perform the next transfer operation while they are %1.
—
CER<BOOKMARK:cer> - Channel Error Register (+0x01)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | ERROR CODE | ||||||
| Bit 4~0 | Error Code |
|---|---|
| %00000 | No error |
| %00001 | Configuration error |
| %00010 | Operation timing error |
| %00011 | Unused |
| %001rr | Address error |
| %011rr | Count error |
| %10000 | External forced stop |
| %10001 | Software forced stop |
—
DCR<BOOKMARK:dcr> - Device Control Register (+0x04)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| XRM | DTYP | DPS | 0 | PCL | |||
| Bits | Description |
|---|---|
| 7~6 | %00: Burst transfer mode %01: Undefined %10: Cycle steal mode without hold %11 Cycle steal mode with hold |
| 5~4 | Dual Address Mode: %00: 68000 bus mode %01: 6800 bus mode Single Address Mode %10: Device with ACK %11: Device with ACK and READY Note: Use in dual address mode (normally %00) |
| 3 | DPS - Device port size %0: 8-bit port %1: 16-bit port |
| 2 | 0 |
| 1~0 | PCL - Peripheral control line %00: Status input %01: Status input with interrupt %10: 1/8 pulse start %11: ABORT input (forced termination) |
—
OCR<BOOKMARK:ocr> - Operation Control Register (+0x05)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| DIR | BIT | SIZE | CHAIN | REQG | |||
| Bits | Description |
|---|---|
| 7 | DIR - Direction %0: Memory→Device (MAR→DAR) %1: Device→Memory (DAR→MAR) |
| 8 | BTD - Multiple block transfer DONE %0: Normal operation %1: If there is a DONE signal, forcibly transfer the next block. |
| 5~4 | SIZE - Operand size %00: Byte (8-bits) %01: Word (16-bits) %10: Longword (32-bits) %11: No pack size. Port size 8-bits. Byte (8-bits) transfer |
| 3~2 | CHAIN - Chaining mode %00: No chain %01: Unused $10: Array chaining %11: Link array chaining |
| 1~0 | REQG - Request generation method %00: Speed limit auto request %01: Max speed auto request %10: External transfer request (by REQ line) %11: Auto request first transfer, external request from second transfer onward. |
Note: Channel #0, #1, and #3 should be used with external transfer request.
—
SCR<BOOKMARK:scr> - Sequence Control Register (+0x06)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | MAC | DAC | |||||
| Bits | Description |
|---|---|
| 7~4 | 0 |
| 3~2 | MAC - Memory address count %00: Do not change memory address register %01: Increment memory address register each time transfer is done %10: Decrement memory address register each time transfer is done %11: Unused |
| 1~0 | DAC - Device address count %00: Do not change device address register %01: Increment device address register each time transfer is done %10: Decrement device address register each time transfer is done %11: Unused |
—
CCR<BOOKMARK:ccr> - Channel Control Register (+0x07)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| STR | CNT | HLT | SAB | INT | 0 | ||
| Bits | Description |
|---|---|
| 7 | STR - Start operation %1: Start operation |
| 6 | CNT - Continue operation %0: No continuous operation %1: Continuous operation |
| 5 | HLT - Halt operation %1: Pause channel |
| 4 | SAB - Software abort %1: Stop channel |
| 3 | INT - Interrupt enable %0: Enable interrupt %1: Disable interrupt |
| 2~0 | 0 |
—
MTC<BOOKMARK:mtc> - Memory Transfer Counter (+0x0A)
Number of transfer operands.
—
MAR<BOOKMARK:mar> - Memory Address Register (+0x0C)
Start memory transfer address.
—
DAR<BOOKMARK:DAR> - Device Address Register (+0x14)
Start device transfer adddress.
—
BTC<BOOKMARK:BTC> - Base Transfer Counter (+0x1A)
Number of transfer blocks (the number of transfer information tables) in array chain mode.
—
BAR<BOOKMARK:BAR> - Base Address Register (+0x1C)
Start address of the transfer information table in array chain/link array chain mode.
—
NIC<BOOKMARK:niv> - Normal Interrupt Vector (+0x25)
Vector number to be used for interrupt generated when CSR ERR is %0.
—
EIV<BOOKMARK:eiv> - Error Interrupt Vector (+0x27)
Vector number to be used for the interrupt generated when CSR ERR is %1.
—
MFC<BOOKMARK:mfc> - Memory Function Code (+0x29)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | FC2 | FC1 | FC0 | ||||
| Bits | Description |
|---|---|
| 7~3 | 0 |
| 2~0 | Memory function code %000: Unused %001: User data %010: User program %011: Unused %100: Unused %101: Supervisor data %110: Supervisor program %111: Interrupt acknowledge |
—
CPR<BOOKMARK:cpr> - Channel Priority Register (+0x2D)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | CP | ||||||
| Bits | Description |
|---|---|
| 7~2 | 0 |
| 1~0 | CP - Channel priority %00: Highest priority %01: Second highest priority %10: Third highest priority %11: Lowest priority |
—
DFC<BOOKMARK:DFC> - Device Function Code (+0x31) Same as MFC.
—
BFC<BOOKMARK:BFC> - Base Function Code (+0x39) Same as MFC.
—
GCR<BOOKMARK:GCR> - General Control Register (+0x3F)
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|
| 0 | BT | BR | |||||
| Bits | Description |
|---|---|
| 7~4 | 0 |
| 3~2 | BT - Burst time Number of DMA clock cycles per burst. %00: 16 clocks %01: 32 clocks %10: 64 clocks %11: 129 clocks |
| 1~0 | BR - Bandwidth threshold (band occupancy) %00: 50% %01: 25% %10: 12.5% %11: 6.25% Note: Only affects channels set to limited speed auto request mode |